This invention relates to electronic circuits and, more particularly, to general purpose test systems capable of testing very large scale integrated (VLSI) circuits, including microprocessors, logic arrays, and multi-chip assemblies, at high speeds. Specifically, the invention is directed to a method and apparatus for automatically testing one or more electrical properties of a series of electronic circuits by monitoring response signals during testing of the electronic circuits in an automated electronic test system.
In automated electronic test equipment, one or more electrical signal sources is coupled to the pins or other nodes at the inputs of an electronic device being tested to force stimuli signals controlled by a test system computer onto the device under test, and the resultant conditions at the outputs of the device being tested are monitored. Typically, the stimuli signals represent logic states or analog voltages or currents which are applied in a parallel pattern to the input pins of the device under test, and the resulting output pattern is checked in parallel.
The signal sources apply stimuli signals to the device under test through pin electronics interface circuits which function as computer controlled interface circuits between the computer of the test system and the individual pins of the device being tested. The pin electronics interface circuits receive these stimuli signals and then through input drivers included in the pin electronics interface circuits switch these stimuli signals onto the desired input pins of the device under test in accordance with a stored program in the test system. The pin electronics interface circuits also receive reference voltages or currents which comparator circuits included in the pin electronics interface circuits compare to the voltages or currents received from the output pins of the device being tested. The output signals from the comparator circuits are returned to the test system computer where they are checked in accordance with a stored program for the proper responses. In this manner, electronic components, for example, semiconductor memories or other integrated circuits, can be individually tested to assure that they meet whatever standard or specifications the ultimate user of the integrated circuit desires.
One disadvantage in the operation of such automated electronic test equipment is the analog settling time. The length of the analog settling time can significantly slow parametric tests when a low current is forced. To set a specified current force condition of test, the programmable load (source or sink current) is applied while voltage comparators sense the limit of test. This current force/voltage measure type of test simulates typical high speed pin electronics interface circuit function at static rather than higher functional test rates allowing accuracy to the minimum resolution step of the voltage and current levels used. When the measurement parameter is a current with a voltage condition of test to be forced, the programmable load current is again used as the test forcing function. In this case, the forced current develops a load dependent voltage at the device under test, and voltage comparators are used to sense if this voltage is above or below the intended condition of test for a pass/fail decision. This procedure assures measurement accuracies to the minimum resolution step, where similar application of the same circuitry at high speed functional rates results in waveform aberrations that reduce the measurement resolution possible.
Mode reconfiguration switching and low current ranges typically limit analog speed to that required to maintain stable operation with a maximum specified capacitive load. This compensates for a worst case slow dynamic response.
Precision measurement unit per pin tests are restricted to the range extremes and minimum resolution of the pin electronics interface circuits which have been optimized for high speed functional testing. With pulse aberrations common on high speed waveforms, the minimum resolution step is likely to be greater than desired for some static measurements. Further restrictions occur when pin electronics interface circuit levels are generated in the test system computer and multiplex switched to groups of pin electronics interface circuit channels. This type of architecture is slower in analog settling due to the long cable from the computer of the test system to the test head and also presents a time consuming software burden to arrive at a measured value per device under test pin. Distributing pin electronics interface circuit levels via a multiplex switch from test system computer modules requires long analog settling times and limits practical precision measurement unit per pin function to go/no-go limit tests.
It is desirable that analog slew rate not be limited to the worst case programmed range and reactive load combination. This can be referred to as an unconditionally stable source but typically results in an unconditionally slow one. Since stable operation with various capacitive loads is required, the technique commonly employed for optimum test speed is to allow programmable loop rolloff, thereby matching the digitally programmed source dynamic characteristic to the test range and load conditions.
Limited current overshoot during slew is desirable to enhance test speed, but voltage overshoot can damage the device being tested. While known digitally programmed sources have some capability to respond to sudden current demand changes, their worst case compensated slow dynamic response can allow damaging transients to occur.